(A) Field of the Invention
The present invention relates to a chip package, particularly to a chip package having reduced wiring layers of a substrate.
(B) Description of the Related Art
In IC packages, multi-layer substrates are widely implemented for chip carriers and for electrical connections. However, the substrate cost is about 30% of the overall package cost, and the substrate cost increases as the wiring layers increase.
As shown in FIG. 1, a conventional IC package 100 primarily comprises a substrate 110, a die-attaching layer 120, a chip 130, and a plurality of electrical connecting components 140. The substrate 100 has a top surface 111, a bottom surface 112, and a plurality of inner fingers 113 disposed on the top surface 111. The back surface 132 of the chip 130 is attached to the top surface 111 of the substrate 110 by the die-attaching layer 120. A plurality of bonding pads 133 are disposed on the active surface 131 of the chip 130 wherein the bonding pads 133 of the chip 130 are electrically connected to the inner fingers 113 of the substrate 110 by the electrical connecting components 140 such as bonding wires. An encapsulant 150 is formed on the top surface 111 of the substrate 110 to encapsulate the chip 130 and the electrical connecting components 140. The IC package 100 further comprises a plurality of external terminals 160 disposed on the bottom surface 112 of the substrate 110 for external electrical connections. Before packaging, the substrate 100 must be fabricated to have all required wiring layers and vias; therefore, the substrate cost cannot be effectively reduced.